Server/External PCIE Connectivity Worksteam: Difference between revisions
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Main Folder: https://drive.google.com/drive/folders/0AJSSbhm5kNnuUk9PVA | Main Folder: https://drive.google.com/drive/folders/0AJSSbhm5kNnuUk9PVA | ||
Draft Document: https://docs.google.com/document/d/1qN52eC0YUnau0Pm4ysk9f84x6p7zmYlx/edit?usp=sharing&ouid=106233237840643362136&rtpof=true&sd=true | Draft Requirements Document: https://docs.google.com/document/d/1qN52eC0YUnau0Pm4ysk9f84x6p7zmYlx/edit# | ||
Latest Slides: https://docs.google.com/presentation/d/1ETPGjzm-Fm9BI3SkCq_vbPSvlWvFWO2Z/edit?usp=sharing&ouid=106233237840643362136&rtpof=true&sd=true | |||
===Past External PCIE Connectivity Events=== | ===Past External PCIE Connectivity Events=== | ||
* [https://www.youtube.com/watch?v=QXOfYpAlXec 23 January 2023 Call] | |||
* [https://www.youtube.com/watch?v=KutrMuxOm3E 9 January 2023 Call] | * [https://www.youtube.com/watch?v=KutrMuxOm3E 9 January 2023 Call] | ||
* [https://www.youtube.com/watch?v=uBlDEFu37ug 19 December 2022 Call] | * [https://www.youtube.com/watch?v=uBlDEFu37ug 19 December 2022 Call] | ||
* [https://www.youtube.com/watch?v=J-VcopXybws 12 December 2022 Call] | * [https://www.youtube.com/watch?v=J-VcopXybws 12 December 2022 Call] | ||
* [https://www.youtube.com/watch?v=fVB-YdJ-D7g 05 December 2022 Call] | * [https://www.youtube.com/watch?v=fVB-YdJ-D7g 05 December 2022 Call] | ||
Latest revision as of 02:17, 7 February 2023
Welcome to the OCP External PCIE Connectivity WIKI[edit]
External PCIE Connectivity is a Worksteam within the Server Project.
Leadership[edit]
Public Mailing List[edit]
- Page: https://ocp-all.groups.io/g/ocp-external-pcie-connectivity/
- Post: ocp-external-pcie-connectivity@OCP-All.groups.io
- Subscribe: ocp-external-pcie-connectivity+subscribe@OCP-All.groups.io
- Unsubscribe: ocp-external-pcie-connectivity+unsubscribe@OCP-All.groups.io
Scope[edit]
To document the various industry usage-model scenarios and requirements for rack-level disaggregated NVMe and/or CXL inter-connected Compute, Acceleration, Memory and Storage modules using PCIe Gen5 & Gen6 external Direct Attached(DAC), Active Electrical(AEC) and Active Optical(AOC) Cables. The Workstream will not explore any specific implementation solutions at this time; however, a future industry standards committee will be formed by willing members aiming to materialize the requirement output of this Workstream into a complete standard cabling specification.
Documents[edit]
Main Folder: https://drive.google.com/drive/folders/0AJSSbhm5kNnuUk9PVA
Draft Requirements Document: https://docs.google.com/document/d/1qN52eC0YUnau0Pm4ysk9f84x6p7zmYlx/edit#
Latest Slides: https://docs.google.com/presentation/d/1ETPGjzm-Fm9BI3SkCq_vbPSvlWvFWO2Z/edit?usp=sharing&ouid=106233237840643362136&rtpof=true&sd=true