Server/External PCIE Connectivity Worksteam: Difference between revisions
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* [mailto:mohamad.elbatal@ocproject.net Mohamad Elbatal] | * [mailto:mohamad.elbatal@ocproject.net Mohamad Elbatal] | ||
===Public Mailing List=== | |||
Page: [https://ocp-all.groups.io/g/ocp-external-pcie-connectivity/ https://ocp-all.groups.io/g/ocp-external-pcie-connectivity/] | |||
Post: [mailto:ocp-external-pcie-connectivity@OCP-All.groups.io ocp-external-pcie-connectivity@OCP-All.groups.io] | |||
Subscribe: [mailto:ocp-external-pcie-connectivity+subscribe@OCP-All.groups.io ocp-external-pcie-connectivity+subscribe@OCP-All.groups.io] | |||
Unsubscribe: [mailto:ocp-external-pcie-connectivity+unsubscribe@OCP-All.groups.io ocp-external-pcie-connectivity+unsubscribe@OCP-All.groups.io] | |||
===Scope=== | ===Scope=== | ||
Revision as of 19:39, 2 December 2022
Welcome to the OCP M-FLW WIKI
External PCIE Connectivity is a Worksteam within the Server Project.
Leadership
Public Mailing List
Page: https://ocp-all.groups.io/g/ocp-external-pcie-connectivity/ Post: ocp-external-pcie-connectivity@OCP-All.groups.io Subscribe: ocp-external-pcie-connectivity+subscribe@OCP-All.groups.io Unsubscribe: ocp-external-pcie-connectivity+unsubscribe@OCP-All.groups.io
Scope
To document the various industry usage-model scenarios and requirements for rack-level disaggregated NVMe and/or CXL inter-connected Compute, Acceleration, Memory and Storage modules using PCIe Gen5 & Gen6 external Direct Attached(DAC), Active Electrical(AEC) and Active Optical(AOC) Cables. The Workstream will not explore any specific implementation solutions at this time; however, a future industry standards committee will be formed by willing members aiming to materialize the requirement output of this Workstream into a complete standard cabling specification.
Documents
- Coming Soon
Past External PCIE Connectivity Events
- Coming Soon