The Nomination Period for the 2023-2025 Incubation Committee (IC) has ended. Below are the nominees, listed alphabetically by Project and their last name. If only one candidate is listed, that candidate will run unopposed.
Reminder: only Silver, Gold & Platinum members are allowed to vote in Incubation Committee elections. The listed point of contact for each member organization will receive their unique voting key and will have until Auguts 11th, 2023 to vote.
For more information on the election process, click here
Cooling Environments
Steve Mills (Meta)
Bio: Steve Mills is a Mechanical Engineer who has dedicated over 25 years to the development of IT hardware in the enterprise and hyperscale space. He joined Meta in 2012 and is currently a Technical Lead for Open Rack. Prior to Meta, he worked for at Storspeed and DELL Technologies. While at Dell, developing custom solutions for large clients, he was first introduced to Open Compute in 2011. Since then, he has been a champion of OCP as a Lead in Open Compute’s Rack and Power Project for 5 years before moving to the Incubation Committee. He has 47 patents and is an author of 7 contributions to OCP.
Data Center Facility (DCF)
Madhu Iyengar (Google)
Bio: Madhu Iyengar is a Principal Engineer at Google and a lead in innovative product development and path-finding for IT hardware and physical infrastructure, including chip packages, server systems, and data centers. Madhu has led Google’s chip-to-data center liquid cooling research and product development program, yielding the delivery of a breakthrough liquid-cooled high performance Machine Learning IT Systems that has been globally deployed at scale. Madhu is also the co-lead for the Google initiative around industry ecosystem development for data center facilities, as well as a Technical Lead Manager with technical and managerial responsibilities, and with a mission to develop and deliver excellent thermal systems, products, and advanced technologies, with a focus on end-to-end, chip-to-chiller, infrastructure stack optimization and innovation opportunities, in collaboration with cross-functional partners. Prior to working at Google, Madhu was a Hardware Architect/Engineer at Facebook, and a Senior Engineer at IBM. He has co-authored over 115 technical papers in journals and conference proceedings, including papers and books with ASHRAE on Data Centers. Madhu holds more than 290 US Patents in the field of IT hardware and data center infrastructure, is an elected Fellow of the American Society of Mechanical Engineers (ASME), and a Member of IEEE and ASHRAE. Madhu has served as an Associate Editor for the IEEE Electronics Packaging Society CPMT Transactions, for the ASME Journal of Electronic Packaging, and for the ElectronicsCooling Magazine, respectively. He has also served as a voting member of the ASHRAE TC9.9 Mission Critical (Data Center) Facilities committee, and as the General Chair of the 2016 IEEE ITherm Conference. He is currently Chair for Thermal Technical Working Group for IEEE Electronics Packaging Society Roadmap on Heterogeneous Integration. Madhu has a PhD in Mechanical Engineering from the University of Minnesota, and a BE in Mechanical Engineering from the University of Pune, India.
Hardware Management
Anil Agrawal (Meta)
Bio: Over 35 years of working experience as an electrical engineer. Currently working at Meta, Inc as a 'Hardware Systems Engineer' and focusing on 'RAS technology enabling' within the Meta's infrastructure. In 2019, co-founded the 'Hardware Fault Management Incubation' sub-project within the 'OCP Hardware Management' project. It has now grown to 99 members who share the same passion of improving hardware fault handling within the hyperscale cloud infrastructure.
Rama Bhimanadhuni (Microsoft)
Bio: Principal engineering leader working at Microsoft Cloud Hardware Infrastructure Engineering team to support Compute, Storage, HPC and AI/ML workloads Infrastructure.
Thought leader with focus on productizing technology roadmaps and spearheading strategic initiatives by forging collaborative partnerships with key industry stakeholders. Current Open Compute Project (OCP) lead for Hardware Fault Management driving scalable solutions for improving Hardware manageability, availability and Serviceability.
With over two decades of hands-on experience in firmware architecture, fleet quality and debug, hardware telemetry, RAS (Reliability, Availability, and Serviceability), People development and delivering results with cross team collabration. Rama holds 10+ patents and a master's degree in electrical engineering from IIT.
Bio: John has worked over 35 years in the computer industry: architecting, designing and coding. Currently, John is a Principal Engineer at Intel - focused on the manageability of systems and datacenters.
Since John has been OCP's IC Rep to the HW Management Project, existing subprojects have produced spec contributions, and new workstreams have been formed to handle area of work brought forth by the community. The subprojects cover fault management, management modules (e.g. DC-SCM) and rack management interface and implementation. The workstreams include RAS API, interoperable profiles and GPU manageability. John has also championed and supported hardware management in the other projects. For example, the HW Mgmt for Liquid Cooling workstream in the Cooling Environments project.
John has been a member of DMTF - a standards organization focused on manageability standards, since 2004. John was an original member of the Redfish Forum.
Networking
Xin Liu (Microsoft)
Bio: Principal Product Manager at Microsoft
Xu Wang (Meta)
Bio: Xu Wang is currently a Hardware Engineer with Meta Platforms, Inc., Menlo Park, CA, where he works on system architecture design and validation of networking hardware for Meta’s mega-scale data centers including the spine switches (Minipack2/Minipack/Backpack) and the Wedge series rack switches (Wedge400/Wedge100), all of which have been contributed to the OCP. Prior to joining Meta, he designed the system-level and board-level hardware of enterprise firewall products with Fortinet, Inc., Sunnyvale, CA. He also worked on server hardware architecture at Futurewei Technologies, Inc., Santa Clara, CA. Previously, he was a Hardware Manager and a Hardware Engineer with Ribbon Communications Inc., Plano, TX, working on VoIP media gateways. Xu received a B.S. and an M.S. degree in electrical engineering from Tsinghua University, Beijing, China, in 1994 and 1996, respective.
Open System Firmware (OSF)
Jean-Marie Verdun (HPE)
Bio: I am thrilled by computers. I spent a lot of time designing them at architectural and hardware level, and participated to crazy projects, including building up the biggest european super computer in the late 90's. I love to share my knowledge and enable people to design better computers. I am particularly focused on open technologies currently, which includes design tools like FreeCAD, KiCAD, and open source firmware projects like linuxboot and OpenBMC. I used to work for big companies, created a french based startup that I successfully sold to an american company in 2018. I am now part of HPE mainly focused on open platforms, specifically DC-MHS adoption and expansion, as well as OpenSource Firmware which have been enabled at scale on our Gen11 platforms.
Dong Wei (Arm)
Bio: Dong Wei is a Lead Standards Architect and Fellow at Arm. He leads the Arm SystemReady Program. He has significant experience in leading the industry in innovations and standardizations and is a staunch supporter for open source development in Tianocore EDK2, UBoot, LinuxBoot, Coreboot, OpenBMC and Trusted Firmware. He is the Vice President (Chief Executive) of the UEFI Forum and co-chairs its ACPI Working Group. He is a Board member of the PCI SIG and co-chairs its Firmware/Software Working Group. He is a Board member and the Secretary of the CXL Consortium and the UCIe Consortium. He is also a TSC member of the Open Programmable Infrastructure (OPI) standardizing the DPU/IPU devices. He is a Senior Member of IEEE.
Rack & Power
Gopa Parameswaran (Microsoft)
Bio: Principal Hardware Engineer at Microsoft. Hardware architect and designer with close to 30 years of hands on experience developing networking and data center products. Good experience with product development process from concept to production in both large company and startup environments.
Security
Bio: I build and research computer systems. I am the Horizontal Lead for platform Security and the Tech Lead for system software at Google's Technical Infrastructure group. I have led memory management, kernel release, and production mitigation of black swans, including Meltdown and Spectre. I co-founded GridCentric, a virtualization startup, acquired in 2014. From January 2010 to October 2011 I worked in AT&T Labs Research, publishing a number of first-tier academic papers. I got my PhD and MSc from University of Toronto. I got the NSERC Doctoral Prize for 2010, the Eurosys best paper award for 2009, and an NSERC Canada Graduate Scholarship. I got my undergrad in Universidad Nacional del Sur in Bahia Blanca, Argentina
Server
Shane Kavanagh (Microsoft)
Bio: Shane is a Principal Platform Architect at Microsoft. He is the technical lead for the team that defines the architecture for systems that power one of the largest server fleets in the world. He has 20+ years of experience in the design of and architecture of high-density flash and HDD based storage systems and 10+ years of experience designing cloud scale servers Shane was previously a hardware architect at Dell where he was the technical lead for multiple cloud focused storage and server platforms.
Lawrence (Ching-Yu) Lo (Intel)
Bio: Lawrence (Ching-Yu) Lo has over 18 years of experience in server platform design, system architecture, debug and validation. He had served as DataCenter platform application hardware team manager in leading ecosystem partners for pre/early-Silicon PO activities to meet 3.5QTR shipment launch targets at Intel. He contributed to several large customer technical enabling events over the past 13 years. Lawrence currently serves as Cloud System Architect working with CSPs and OxMs on cloud reference design architecture and development in Intel’s datacenter platform and AI group. He recently is focus on the DC-MHS specifications and contributed a modular PRoT architecture with specifications whitepaper.
Bio: AMD - Principal Member of Technical Staff (PMTS), 2022-present
OnLogic - Senior Technologist, 2021-2022
Lenovo/IBM - Principal Engineer, 1998-2021
An accomplished hardware engineer with 25 years of industry experience Greg has made significant contributions and played instrumental roles in the design and development of several cutting-edge server systems throughout his career including:
Platform architect and lead engineer for Lenovo’s Mission Critical High-End portfolio including the SR950 4-8-socket scalable 4U and the SR850P high performance 4-socket/2U
Architect for OnLogic’s Axial AC101, their first edge focused, 1U rack mount capable server.
Architect for OnLogic’s Factor 200 series of Raspberry Pi enabled Industrial edge platforms.
Lead engineer for IBM’s x3690 X5 featuring QPI scaling and MAX5 memory expansion chassis capabilities. IBM’s x330 and x335 1U servers featuring embedded C2T KVM technology.
Currently serving as a Principal Member of Technical Staff within AMD’s Strategy and Architecture team Greg is responsible for working both internally and externally with customers to set hardware expectations and direction for future AMD platforms. Greg excels at early product conceptualization and floor planning and has a broad understanding of all areas of system architecture including high speed IO (PCIe/CXL), memory, network, storage, power and thermal.
From an OCP perspective, since helping AMD to join the OCP Datacenter Modular Hardware System (DC-MHS) workgroup in 2022 Greg has been a vocal member of several sub-workgroups in addition to co-leading the Modular Shared Infrastructure (M-SIF) sub workgroup within DC-MHS. Focused on driving meaningful change within the industry Greg consistently provides valuable, well thought out feedback that remains true to both the governance of DC-MHS and the larger OCP community. Greg is open to differing opinions and takes a very collaborative and inclusive approach to ensure success and continued forward progress.
Jean-Marie Verdun (HPE)
Bio: I am thrilled by computers. I spent a lot of time designing them at architectural and hardware level, and participated to crazy projects, including building up the biggest european super computer in the late 90's. I love to share my knowledge and enable people to design better computers. I am particularly focused on open technologies currently, which includes design tools like FreeCAD, KiCAD, and open source firmware projects like linuxboot and OpenBMC. I used to work for big companies, created a french based startup that I successfully sold to an american company in 2018. I am now part of HPE mainly focused on open platforms, specifically DC-MHS adoption and expansion, as well as OpenSource Firmware which have been enabled at scale on our Gen11 platforms.
Storage
Mike Allison (Samsung)
Bio: I am a Sr. Director in the Samsung DSA Product Planning and Business Enablement team focusing on standards for existing and future products. I am a very actively participating member of standards since 2016 (OCP Storage Project, NVM Express®, DMTF, PCI-SIG, and SNIA) where I have a proven record of reviewing specifications prior to public release. I am developing new OCP processes that include defining a mechanism to allow errata changes to OCP specifications and for protection of IP to allow more open discussions of contributed OCP documents. I am the chair of the NVM Express Errata Task Group, lead author of many technical proposals and errata documents, and was the editor for the NVM Express Base specification 1.4. For over 39 years, I have been an embedded firmware engineer and architect working on systems and simulations for laser beam recorders, fighter aircraft, graphics cards, high-end servers, and am now focusing on Solid State Drives. I hold 31 patents in graphics, servers, and storage. I hold a BSEE/CS degree from the University of Colorado, Boulder.
Swapna Yasarapu (Microsoft)
Bio: Swapna Yasarapu is a distinguished industry leader with over 20 years of experience in driving innovative technologies from conception to widespread adoption. Swapna's expertise lies in engaging customers, setting strategy, defining roadmaps, driving industry standards and initiatives and leading high performing teams to deliver products and new innovative technologies.
After earning her MS in Computer Systems and Software from UC Irvine, Swapna began her career as a design engineer at Western Digital. She quickly advanced to the position of principal engineer and leading project teams. Swapna then transitioned to product strategy and management, while also completing her MBA at UCLA's Anderson School of Management, where she was the valedictorian. Over the next decade, Swapna coauthored “Inside Solid State Drives” book, and rose to a competitive leadership position where she led the datacenter flash SSD product segment at Western Digital Corporation.
Currently, Swapna is a Principal at Microsoft, leading the Azure Storage Platform Strategy & Planning team. Her dedication to innovation and collaboration has been instrumental in shaping the future of storage technology.
Sustainability
Eric Dahlen (Intel)
Bio: Chief Technologist for Cloud in DCAI/CESG. Peer+1 to a highly matrixed architecture team focused on Cloud Service Provider technologies, usage models, and solution architectures. Responsible for mapping existing and emerging customer workloads to system level architecture needs, supporting internal product and technology planning and pathfinding, as well as external disclosure, feedback & evangelization. Over 20 years in server component development, most of it spent on chipset projects and their associated technologies. Parent of a grade-schooler, and lapsed avid golfer.
Shruti Sethi (Microsoft)
Bio: Shruti Sethi is a passionate professional having a deep experience in multiple technological aspects of computing and storage systems. She has years of industry experience in two main domains – Graphics & Storage. She has extensively worked in Graphics power management, workload management, setting performance targets and Data Center storage hardware. She is currently most vested in the intersection of Data Center Technology and Sustainability, driving the next wave of initiatives in this domain for AZURE. Her particular interest is towards making Sustainability a core Strategy for Data Center management. She holds an MS degree in Computer Engineering from Georgia Institute of Technology and an MBA from University of California, Berkeley.
Telco
Craig White (Nokia)
Bio: Professionally, I support the adoption of OCP specifications into the Telco environment. I have worked with the Nokia team to make several Telco/NEBS enhancements to OpenRack including -48V and HVDC inputs into the power shelves, EMI shielding options, and Zone 4 Earthquake certification. Most recently completing work on a Skylake motherboard with support for high packet throughput VNF’s, and also having hot swappable high-speed storage options. I also assist several software teams to validate and develop enhancements to telco related open software stacks on integrated OCP hardware cabinets many based on Openstack and also the VNF’s that run on these stacks. I also have several patents related to core backbone networking.
OCP Community based, I have been involved in the OCP Telco Project since the formation meetings of the group. I was privileged to serve as a founding co-lead of the project and established many of the administrative aspects of the project. It is my belief that open communities are fundamental building blocks towards the future of technology. I have contributed to many IETF RFCs and co-authored several addressing software disaggregation of network link technologies.
Time Appliances Project (TAP)
Elad Wind (Nvidia)
Bio: Business development and growth - driving IP, semiconductor, hardware, software system and turn-key solutions with Tier-1 Cloud Service Providers