Joint OCP & JEDEC Workshop - Standards for Chiplet Design with 3DIC Packaging - Day 2 of 2

This workshop will bring together chip designers, chiplet providers, EDA tool providers, packaging and test houses and foundry partners to discuss developing common data formats, tool interfaces and process flows for a revamped supply chain.

The goal of the workshop is to identify standards that, if developed, can simplify chiplet/3DIC design from specification and tapeout to chip packaging. We envision that interoperable formats will streamline handoffs between design, verification, assembly and packaging tools. Standardized workflows will also facilitate collaboration across organizational boundaries.

Part One can be found here

Standards for Chiplet Design with 3DIC Packaging - Day 2 of 2

Slide Decks

• Coming Soon!